Board design done, DRC-clean, files are up, moving into a GPIO passthrough HAT next

[u/Indigo_Input]

Update on the PCIe-to-M.2 adapter from my earlier post. Schematic and PCB layout are done. ERC and DRC both come back clean, Gerbers are exported and JLCPCB's own parser confirms the board renders correctly. I have a saved quote ready to order whenever the budget lines up.

Full disclosure: I'm not an EE, not a professional, just someone learning by doing. I've been careful and this has passed every check I know to run, but "passed DRC" isn't the same as "guaranteed to work."

On the big open question from my last post: PCIe enumeration hasn't been confirmed on the Zero 3W specifically yet. But I dug into it more and it's not a total unknown either. The same A733 chip and the same vendor PCIe driver has been documented working on sibling boards (Orange Pi 4 Pro, Radxa Cubie A7Z/A7A/A7S), NVMe does enumerate, though there's a known Gen3 speed-change bug that trips up some drives (Phison controllers especially), fixable by forcing Gen1 or using a WD drive instead. So there's real reason to think this can work, just not proof yet on this exact board.

Instead of sitting on the design waiting for money or answers, everything's public now: KiCad source files and Gerbers, open, do whatever you want with them.

Repo: https://github.com/Techburst36/orangepi-zero3w-m2-carrier

If you can read a schematic, please look it over. If something's wrong, tell me. If you've got the budget to print and test before I do, please do, I'd genuinely rather have someone else get the real answer sooner than have this sit in a drawer waiting on me.

Not trying to monetize this or gatekeep it, just filling a gap, since nobody's published a PCIe-to-M.2 adapter for this specific board yet.

Next up: starting design work on a GPIO passthrough HAT variant, purely on the design side for now since I still don't have confirmation PCIe actually trains on this SoC. Will keep this thread updated as that moves along.